2.8. ProFusion Chipset

The next evolution was the ProFusion chipset, shown in Figure 2-8.

Figure 2-8. Intel-based server block diagram.

Jointly developed by HP and Intel, the ProFusion chipset uses a unique two-port (bus) memory design with 1.6GB/s memory bandwidth (2 x 800MB/s), allowing simultaneous access to memory on both ports.

The ProFusion Memory Access Controller (MAC) manages two separate memory controllers on separate memory buses. This technique employs high-speed synchronous DRAM (SDRAM) interleaved on a cache line basis. One controller manages all of the odd cache line addresses, and the other manages all of the even cache line addresses. As a result, latency is reduced when accessing two consecutive cache lines in address order. The MAC arbitrates the access by the two processors on the two main system buses to the memory and I/O system.

The ProFusion Data Interface Buffer (DIB) provides the data path control and buffering between the AGTL+ buses and memory. The DIB consists of buffers between the processor, I/O AGTL+ buses, and memory. If the required dual inline memory module (DIMM) is busy when the MAC initiates a memory cycle, the DIB temporarily stores the address and forwards it to the memory on the next available cycle.