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Explainer on Packaging: Interposers, Bridges and Chiplets

A Conversation with Intel’s Ramune Nagisetty

By   11.10.2020 12

EE Times recently sat down with Ramune Nagisetty, Intel’s packaging maven, to discuss the progress in advanced packaging technologies in recent years, and where Intel sees them going in the future. Here’s what we learned.

The IC industry is clearing its path forward by relying on what was once one of its most mundane tools: packaging. There are several relatively new approaches to IC packaging, and they can all help significantly boost IC-level performance. The great thing is that many of these technologies are mature enough and have been around long enough that they are now accessible to even startups and universities.

While some of these technologies are already being offered by major foundries, one of the newest and most promising — chiplets technology — is still immature. What’s missing that would help advance the state of the art, says Intel’s Ramune Nagisetty, would be the creation of more standardized interfaces for mixing and matching the silicon components in advanced packages.

“The exciting part is lowering the barriers to play in this ecosystem,” she said. “Ten years from now, we’ll see fruits of this approach.”

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Nagisetty is Intel’s packaging maven; her formal title is director of process and product integration at Intel Technology Development. Intel, one of the last bastions of advanced semiconductor process technology in the U.S., has designated advanced packaging technology as one of the keys to its future. In a recent conversation with EE Times, Nagisetty said Intel has a technology roadmap for every one of its packaging vectors, just as it has always had roadmaps for process technology.

Ramune Nagisetty

Packaging was long the least glamorous aspect of the semiconductor business, but about 15 years ago it started becoming apparent that packaging could become a performance bottleneck, but with a bit of innovation, not only could that bottleneck be avoided, but new packaging approaches could actually enhance IC performance.

Intel has been doing this for a while now. The company proposed its Embedded Multi-die Interconnect Bridge (EMIB) technology in 2008 as a way to provide high density interconnect of heterogeneous chips, Nagisetty observed.

EMIB is a variant of 2.5D technology. The common approach to 2.5D packaging is to use a silicon interposer – a layer of silicon with vias that is sandwiched (or “interposed”) between two chips. Intel believes interposers are often physically too large, so its EMIB uses a bridge die with multiple routing layers.

“New technologies need a tipping point before they start getting used,” Nagisetty said. “The inflection point was the rise of disruptive AI architectures based on neural networks.” And it wasn’t just the trend, but a specific event, the ImageNet competition in 2012. “That was an important point – it showed the feasibility of neural networks, and it gave rise to accelerators and high bandwidth memory inside the package – that began the toehold of memory in the package,” she said.

Historically, the general trajectory of the semiconductor industry has been to integrate more and more functions on-chip, but for some advanced IC designs, that was not recommended or not possible.

First, it’s not always possible for a company to put all the circuitry necessary from some applications on one giant die because from a production standpoint, the maximum size of a die is reticle-limited.

“The second point that drives this is the rising design cost for re-use and the need for IP portability for a particular technology node,” Nagisetty noted. “Logic technologies are becoming more specialized, whether for mobile or high performance.” The example she gave was a SerDes; there little if any need to implement a SerDes at the same technology node as the logic in advanced IC designs. More to the point, it’s possible to tailor a technology (e.g., a SerDes) to a technology node.

The SerDes example specifically references Intel’s Stratix FPGAs. Nagisetty said there is a menu of Stratix FPGAs, implemented at six different technology nodes available from three different foundries. “I think Stratix was first with 58 gigabit per second SerDes,” she said. “It allowed us to be more competitive and first to market with the high-speed SerDes.”

In short, there’s a benefit to disaggregation.

The third reason to embrace advanced packaging is to gain agility and flexibility, she said. “The value of mixing and matching chiplets from different technologies is becoming clear.”

Two really good examples, Nagisetty said, are Intel’s Kaby Lake G and Lakefield products.

“With Kaby Lake G we integrated third-party IP inside our package, which allowed us to create a smaller form factor for high performance mobile gaming.” The third-party IP was a Radeon accelerator from AMD.

That was a clear example of using advanced packaging to improve end-use performance, she said.

Where Kaby Lake G used Intel’s EMIB 2.5D approach, Lakefield relies on die stacking – 3D stacking. Intel calls its version of 3D stacking Foveros.

Intel’s Foveros technology

Lakefield, she said, is “an example of how packaging can give you the smallest X-Y footprint. The end user can see the benefit either in the performance or form factor, or both.”

There is a rich set of packaging technologies, and to make things even more interesting, they can be mixed-and-matched. Intel, for example, recently introduced “co-EMIB,” which is a combination of EMIB and Foveros.

Last year Intel introduced two more advanced packaging variations, omni-directional Interconect (ODI), which from an architectural standpoint is a stacking approach that allows for cantilevering chips. There are several benefits including power delivery to the top die in the stack through through-silicon vias (TSVs).

Intel, TSMC and others are working on an approach called copper-to-copper hybrid bonding, yet another variation of stacking that might lead to innovations in 3D ICs and the connecting of so many DRAM chips the combination is being referred to as DRAM cubes.

We asked Nagisetty if there are clear paths for continuously refining these packaging technologies, similar to the way successive production process nodes have always been plotted out.

“There is a packaging technology roadmap for every single one of our packaging vectors,” she responded. “So, we have one for interposer, one for decreasing pitch from 55 microns, going to 36 microns. And 36 is not where we end. Foveros will go to 25. Hybrid bonding will start at 10 and move down in pitch.”

The disaggregation, and associated examples such as Kaby Lake G, have sparked dreams among chip designers of mixing and matching functions from different suppliers – not just one. That’s the key concept of chiplets.

From a commercial standpoint, the chiplets approach makes a lot of sense. The cost of a highly integrated system on a chip (SoC) can be very high — so high it’s prohibitive for many. Furthermore, the complexity of such highly integrated semiconductor systems makes manufacturing more challenging; there is a direct relationship between higher complexity and yield loss.

The U.S. Department of Defense is interested for those reasons and others. The Defense Advanced Research Projects Agency (DARPA) is supporting a program to encourage the market for chiplets. This is DARPA’s take on the technology:

The monolithic nature of state-of-the-art SoCs is not always acceptable for Department of Defense (DoD) or other low-volume applications due to factors such as high initial prototype costs and requirements for alternative material sets. To enhance overall system flexibility and reduce design time for next-generation products, the Common Heterogeneous Integration and Intellectual Property (IP) Reuse Strategies (CHIPS) program seeks to establish a new paradigm in IP reuse.

Turning to chiplets can significantly reduce cost, compared to a more complex SoC. This graphic was presented by AMD’s Lisa Su in a paper delivered at the IEDM conference in 2017 and reproduced by the Open Compute Project.

[There are two distinct programs using the acronym CHIPS. They are separate, but exacerbating possible confusion, they are congruent. Congress has proposed a bill called the Creating Helpful Incentives to Produce Semiconductors for America Act. The CHIPS for America Act does allocate funding specifically for advanced packaging research, but it does not specifically mention DARPA’s CHIPS program.]

Intel is, of course, participating in DARPA’s CHIPS program. “The Stratix FPGA is sort of the hub of that,” Nagisetty noted.

The key to success – of the CHIPS program specifically and of chiplets technology in general – is going to be the creation of more standardized interfaces so that chiplets from other companies can be connected.

To that end, Intel has contributed an interconnect technology called the advanced interface bus (AIB), which the company created in 2018. Starting in 2019, Intel has been making AIB available with a royalty-free license. (It can be found on GitHub.)

“This is the seed and toehold of what I believe will develop into an ecosystem, and innovation will be unlocked,” Nagisetty said. “It will be similar to the way boards developed –where have things like PCI Express – that allows companies to build products based on an interface standard.”

It’s early days, and there’s a lot of complexity to deal with, and also business models that need to be worked out,” she continued, “but what I love about it is that people can participate in this ecosystem. Before, the barrier was really high. But now, there are some startups and universities participating.”

Still, a body helping to shepherd the creation of standards around chiplets technology would be not just useful, but “critical,” Nagisetty said. “If I could fast-forward in time, this would be taken care of. AIB has been the best so far, but there’s more to be done. That’s where I would wish for more effort.”

One organization that is taking its first tentative steps toward filling that void is the Open Compute Project (OCP), which has a fledgling program proposing the development of an open domain specific accelerator (ODSA).

The Open Compute Project (OCP) says the conclusion from this projection from IHS Markit is that there is an “Immediate opportunity for chiplets and an open interface.” [Click directly on the graph for a larger view.]
It might not be immediately obvious how a group concerned directly with data center server technology gets so intimately involved with chiplets. The OCP starts with the observation that there will be an ongoing proliferation of new workloads that data centers will have to handle. Currently, the best solution for optimizing silicon systems for any given new workload is to create an SoC. But – as noted above – that gets expensive. One way of reducing the cost of silicon systems for emerging workloads would be to use chiplets technology – and that’s how the OCP gets involved with chiplets.

Today, different companies exploring chiplets technology tend to rely at least in part on  internally-developed design tools, and all chiplets interfaces are proprietary, according to the OCP. “ODSA seeks to democratize this evolution of chiplet and SIP [system in package] technology for the larger mass market through an open eco-system marketplace,” according to an OCP document called Intro to ODSA, which can be accessed from this page.

12 comments
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chipmonk0   2020-11-11 11:56:15

Some really IGNORANT & ARROGANT comments here by Brian Santo ( Editor in Chief of EE Times no less ! ) on Packaging & it’s impact on Semiconductor integration. Makes one skeptical about the quality of EE Times these days !

Many Johnny come Latelies in the semiconductor TRADE media have jumped on the Packaging bandwagon and are merely parroting one another w/o taking trouble to understand either its history ( past contributions ) or future challenges.

There is very little silicon Fab competence left in Silicon Valley and the Fabless Co.s there have allowed themselves to become hopelessly dependent on their Offshore Foundries and in the process have undermined US Competitiveness and National Security !

WHAT A SHAME !!

So here is a remedial history lesson on the contribution of Adv. Packaging to Semiconductor INTEGRATION for irresponsible LOUDMOUTHS as well as the Designers in the Fabless co.s swayed by the self serving propaganda of their Offshore Foundries and in the process have harmed the US based semiconductor industry.

HISTORY :

More than 30 years ago IBM started using Integration at Package level ( so called MCMs ) when their Fabs could n’t keep up with Intel etc. ( with larger volumes and income ) in the Moore’s Law March. The rationale, strategy and essential components of the MCM technology were reused in 2011 by an Offshore Foundry ( but NOT acknowledged, in fact covered up with a new name so as to mislead the naive Designers of Silicon Valley, IGNORANT not only of Adv. Packaging, but most aspects of Fab Front End processes as well ) when confronted with the challenge of making large FPGA chips in spite of the low yields of their then immature 28 nm process.

(2) Most development of Adv. Packaging technologies and their applications for the last 30 years have been done in PHOENIX AZ USA by two IDMs ( Motorola SPS and then Intel ) and since the early 1990s have been applied to high volume products both single chip ( CPUs, Adv. Pkg. enabled Multi processor architectures on a single chip ) and multi chip ( Servers ). Adv. Packaging technologies ( more capable but cheaper than those used by IBM ) developed at the R&D labs of the two leading IDMs ( Moto and Intel ) in PHOENIX gradually diffused out to Offshore Foundries through OSATs who maintained surveillance units in Phoenix and by the early 2000s became available to the FABLESS WONDERS of Silicon Valley.

FUTURE :

There is a frantic naming and renaming ( 2.5 d, Heterogeneous Integration, Chiplets, ... ) of Adv. Packaging technologies now going on in the Silicon less Silicon Valley ( old wine in new bottles ? ) by newcomers but most of the fundamental work to identify real problems and resolve them is still going on in PHOENIX, AZ.

Provided a library of integratable & testable Chiplets can be built up, Chiplets could become a viable approach to reduce Time to Market and first cost related barriers to entry. But that would be just as easy to implement by Foundries, specially those that have pulled ahead of IDMs, just Chiplets are NOT a long term Panacea for IDMs just as IBMs MCM technology could not save their Fabs.

To get an understanding of the theoretical issues and challenges that have guided the efficient development of Adv. Packaging over the last 30 years and is now guiding its future technology ROADMAP, Johnny come Lately journalists as well as the Designers in Silicon less Silicon Valley would do well to consult the IEEE IRDS semiconductor roadmap.

Brian Santo   2020-11-11 13:21:55

One of your points was to insult me personally. Good so far -- I got that. Were you trying to make a point about advanced packaging technology? Because that was less clear. Also, are you a member of the PHOENIX AZ Chamber of Commerce, by any chance? -- Brian Santo

chipmonk0   2020-11-12 13:22:36

As a reader of EE Times for over 30 years I had expected a better informed, more original & in depth article, especially from its current Editor in Chief.

No I am NOT a member of the Phx Chamber of Commerce, but merely the inventor ( at Moto & Intel ) of most ( about 80 % ) of the Adv. Packaging technologies ( Flip Chip including the version that is now used to build 3d stack of dies, the special robotic tools to assemble them ). Managed their transition to High Volume Manufacturing as well. Those later Flip Chip technologies have replaced the original IBM version and have now become the industry standard ( worth about $25 billion a year of value added to the $400 billion Semiconductor industry, though now done mostly in Taiwan & SoK ).

Also happen to Chair the “Packaging Integration” section of the IEEE IRDS Semiconductor Roadmap.

The IGNORANT & ARROGANT denizens of the Silicon less Silicon Valley have caused serious harm to US competitiveness by facilitating the siphoning off of US developed technologies. It’s time to STOP.

Hope that for the sake of historic and technical accuracy, EE Times too will be more responsible in its opinions.

sd/ Dr. ChipMonk

Brian Santo   2020-11-12 13:58:43

You have impeccable credentials, and yet you still haven't made a substantive point. Are you saying that the hyperscalers and other data center operators working through the Open Compute Project are... what? Lying about their interest in chiplets? Are you saying that Intel and AMD are pursuing various advanced packaging technologies even though their customers don't want them? Are you saying the Darpa is wrong to be interested in chiplets? Which companies, specifically, are "facilitating the siphoning off of US developed technologies," and how are they doing it?

chipmonk0   2020-11-12 15:45:34

Brian :

I see that your dander is up. Given that, there is really no point in trying to reply to your questions, also because the answers should be self evident. Let me just say that the two largest Fabless co.s in CA have been giving over $10 billion a year of business to their Offshore Foundry. Sooner or later that starts to make a difference including how those Offshore outfits spend their Loot not just for R&D but also to buy influence opinion among the mercenaries in this country. However, to be fair US based IDMs and Fabs too have caused themselves a lot of SELF INFLICTED wounds. The sole Foundry still based in the US ( w/ their latest Fab in NY State ) dropped out of the 7 nm race because they are headed by far too many people from IBM Fabs who had already thrown in the towel in keeping up with Moore’s Law. For the last decade or so the sole credible IDM left standing in the US ( w/ their R&D for Device and Architecture based in YOUR hometown but that for Packaging in MY hometown ) has been hobbled by its own BoD ( dominated by Finance types ) who kept selecting Economists, non PhD Chemists and now Finance guys to lead and motivate Technologists, unqualified CEOs who totally missed major market upheavals like the advent of low power SoCs for Smart Phones and have now allowed even its once fabled manufacturing prowess to FAIL ( low yields at 7 nm ) for all the world to see ! What the US now needs to regain strategic competitiveness is not just Chiplets and their ancillaries ( like a standardized & universal yet not too inefficient Interconnect Mesh ), but since now DARPA too understands that like IBM’s MCM technology, Chiplets too are only a stopgap, ALSO more Hardware MACHO in the US. But no amount of crash programs ( SemaTech II ? ) can restore US lead so long as the FABLESS WONDERS of the Silicon less Silicon Valley and their Apologists in the Trade press keep aiding & abetting the Offshore Foundries.

Brian Santo   2020-11-12 19:52:11

You are miserable at detecting dander, but that doesn't diminish your impressive technical credentials. As near as I can reconstruct it, you are angry that U.S. semiconductor companies have given up their fabs. Other industrial companies in the U.S. have been offshoring their factories (if they retain them at all), but IC companies would be different if it weren't for IBM, all of the chip companies in Silicon Valley, and the parts of Intel that are not in Arizona.

You're not going to tell us what is bothering you about advanced packaging technology because, whatever it is, it is so self-evident that you cannot bring yourself to repeat it.

And the deteriorating trade press is abetting... whatever it is that is so self-evident you can't talk about it.

Is that right?

The button for caps-lock is on the far right of your keyboard, in case you want to emphasize your entire response instead of just shouting highly technical terms such as "arrogant" and "macho."

chipmonk0   2020-11-14 12:16:43

I do not think EE Times have been well served with your Ignorant Rants and Shoot from the Hip rejoinders. So here are a few more comments for the benefit of your readers interested in Advanced Packaging ( AP ) and Package Level Integration ( PIL ) and their future.

The implementation of AP technologies to bring to market new PIL based products ( like 2.5d, HBM, EMIB, FOVEROS etc. ) could be so effortless and rapid ( just 2 years ) ONLY because the technology needs had already been anticipated and developed at the world’s leading AP R&D based in Phx, AZ for the last 3 decades.

Continuous Improvement of AP to enable Chiplets and Die Stacking are ongoing in Phx

It must be realized however that AP will still remain a temporary fix for Fab deficiencies, especially when it comes to high volume products. Fabs that still have the financial resources ( about $ 10 to 15 billion ) and the ability to attract at least 150 of the best new PhDs ( in Math to Mat’l Sci. ) and retain them for 5 years, must emulate the Offshore Foundry that in 2010 had to resort to AP based PIL as a temp. fix but kept upgrading their Fab capabilities and now pulled ahead of the once leading IDM, rather than fall into the same SELF DELUSIONAL TRAP as IBM did with their MCMs.

To get into the theoretical basis and details behind future strategies look up the IEEE roadmap for Semiconductors.

chipmonk0   2020-11-14 12:44:49

Nothing AT ALL bothers me about Adv. Packaging ( AP ) technologies because it had anticipated the technology needs of the current round of Package Level Integration ( PIL ) when Fabs stumble, which is the reason why the development and Time to Market for new products ( 2.5d, HBM, EMIB, FOVEROS etc ) based on PIL have been so effortless and rapid

But GREENHORNs in the now Silicon less Silicon Valley and even IDMs have gotten carried away w/ this easy success and are OVER HYPING it.

( Continuous Improvement of AP technologies to enable Chiplets, Die Stacks are in progress in Phx, the WORLD LEADER for AP for the last 3 decades ).

Nevertheless PIL by using even the latest AP is only a temporary fix, especially when it comes to high volume single chip products ( CPUs, SoCs .. ).

To retain that segment IDMs must avoid IBMs SELF DELUSIONAL failed strategy of MCMs, but while they still have a few 10s of billion $s left in the Bank, MUST URGENTLY follow that of the Offshore Foundry that has now overtaken them ( use AP only as a temporary respite when leading edge Fab process is immature, but then KEEP PUSHING the Fab ).

To understand the theoretical basis for this PROVEN STRATEGY the underserved readers of EE Times interested in Integration ( ON chip vs OFF Chip e,g by PIL ) should look up the IEEE Roadmap for Semiconductor Devices.

Brian Santo   2020-11-15 15:25:23

So you are saying that TSMC has manufacturing deficiencies and that's why it is developing chiplets with its customers?

chipmonk0   2020-11-16 11:58:53

No I am certainly NOT !

But what makes you jump to that conclusion ? Do not know when to quit even when LICKED ? Hopelessly Dense ?

TSMC now has a stable 5 nm ( by their own definition of CDs, equivalent to the still immature 7 nm process at Intel ) FinFET process for both Portables as well as Power hungry High Perf.

They can cater to the needs of at least two classes of customers :

1. Those w/ very large volume ( > $ 10 billion per year ) single design e,g. battery operated SoCs, the largest 2 of such Customers are in CA

2. Customers w/ much smaller volume who require flexible & powerful designs e,g. tight integration between Processor and DRAM ( process incompatible / uneconomic for integration on a single chip ), at least 4 such medium size ( $2 to 5 billion per year ) Customers in the Silicon less Silicon Valley )

But for new / very small ( << $ 1 billion a year ) customers ( start up Design groups w/ innovative designs in emerging applications like AI ) for who NREs for the above two approaches would be prohibitive ( both First Cost as well as Time to Market wise ), Chiplets integrated by the densest of Adv. Packaging technologies ( Package Level Integration ) that allow leveraging existing libraries combined w/ some last minute customization to boost specific aspects of say a proprietary algorithm, would be the way to go.

So Doug, Mirng Ji, SP etc. who learnt it all ( starting w/ getting their PhDs ) here in the US are making their crews work diligently on all the options including pushing AP and PLI. They are soon coming back to AZ ( read recent TSMC announcements ) to get fresh ideas.

While the BS Polygon Pushers on the West Coast, hooked on ordering out for Pizzas since their UG days, now do the same for even Chips.

Adios
sd/ Dr. ChipMonk

Brian Santo   2020-11-16 13:13:37

If you have a colleague who can write an article about the IEEE Roadmap for Semiconductor Devices -- and to what extent different companies are, or are not, conforming to it -- that proceeds logically and keeps the insults and ALL-CAPS RANTING to a minimum, then EE Times would be pleased to consider publishing it.

chipmonk0   2020-11-17 10:41:45

EE Times probably still has a large no. of technically qualified readers. But why would any bonafide technologist ever spend the time to address even that readership if they have to go through an Editor in Chief such as yourself ?? The evidence is all there in your original article and subsequent response to my posts.

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